1. Field of the Invention
This invention relates to a method of suppressing junction capacitance of source/drain regions, and more particularly to a method of forming the source/drain regions by double implantation.
2.Description of the Related Art
The functioning speed of a transistor can be speed up by shortening channel length while downsizing the MOS devices. The Lightly Doped Drain (LDD) structure is widely used for solving the problem of abnormal function or even dysfunction of a transistor caused by the Short Channel Effect (SCE) and the Hot Electron Effect (HEE) that occur when the channel length is overly shortened. In the method of forming source/drain regions by only one ion implantation step, arsenic ions are widely used. Because arsenic ions are similar to silicon ions in radius, fewer dislocations will be formed when arsenic ions are doped into a silicon substrate. However, as the doping energy increases, dislocations occur even using arsenic ions as dopants.
FIGS. 1A-1B are cross-sectional views illustrating the fabrication of a MOS transistor in accordance with the prior art;
As shown in FIG. 1A, thermal oxidation is used to form a gate oxide layer 11 on the substrate 10, followed by subsequent deposition of polysilicon and tungsten silicide, after which a gate 12 is defined. Using the gate 12 as a mask, arsenic ions are implanted into the substrate 10 to form a lightly doped drain. The substrate 10 is then placed in a thermal diffusion oven to form the lightly doped regions 16.
As shown in FIG. 1B, silicon dioxide is deposited by chemical vapor deposition (CVD) to cover the substrate 10 and the gate 12. Portions of the silicon dioxide layer are then etched back to form spacers 14 on the sidewalls of the gate 12.
Referring to FIG. 1C, arsenic ions are heavily and deeply implanted into the substrate while using the gate 12 and the spacers 14 as a mask. The wafer is then annealed to form source/drain regions 18. Typically, the source/drain regions 18 have a different conductive type from conductive type of the substrate 10. As the source/drain regions 18 are formed in contact with the substrate 10, a P-N junction is formed. At P-N junction, holes from P-side diffuse into the N-side, while electrons from N-side diffuse into the P-side. As a consequence, an internal field is built, and a depletion region is formed. The depletion region is electrically neutral. The depletion region plays a role as a dielectric layer within two electrodes, and this structure causes the junction capacitance.
The junction capacitance depends on the width of depletion regions, and the width of depletion regions is related to the junction profile of the implanted ions in the substrate. Because of the abrupt junction profile of arsenic ions, the width of the depletion region is narrow, and the junction capacitance become large. In other words, the high-energy implanted arsenic ions create defects in the silicon crystal structure of the substrate and this causes some leakage in the source/drain regions 18.